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ISL6740, ISL6741
Data Sheet January 2004 FN9111.2
Flexible Double Ended Voltage and Current Mode PWM Controllers
The ISL6740, ISL6741 family of adjustable frequency, low power, pulse width modulating (PWM) voltage mode (ISL6740) and current mode (ISL6741) controllers is designed for a wide range of power conversion applications using half-bridge, full bridge, and push-pull configurations. These controllers provide an extremely flexible oscillator that allows precise control of frequency, duty cycle, and deadtime. This advanced BiCMOS design features low operating current, adjustable switching frequency up to 1MHz, adjustable soft start, internal and external over temperature protection, fault annunciation, and a bidirectional SYNC signal that allows the oscillator to be locked to paralleled units or to an external clock for noise sensitive applications.
Features
* Precision Duty Cycle and Deadtime Control * 95A Startup Current * Adjustable Delayed Over Current Shutdown and Re-Start (ISL6740) * Adjustable Short Circuit Shutdown and Re-Start * Adjustable Oscillator Frequency Up to 2MHz * Bidirectional Synchronization * Inhibit Signal * Internal Over Temperature Protection * System Over Temperature Protection Using a Thermistor or Sensor * Adjustable Soft Start * Adjustable input Under Voltage Lockout
PKG. DWG. #
Ordering Information
PART NUMBER ISL6740IB ISL6740IV ISL6741IB ISL6741IV TEMP. RANGE (oC) -40 to 105 -40 to 105 -40 to 105 -40 to 105 PACKAGE 16 Ld SOIC 16 Ld TSSOP 16 Ld SOIC 16 Ld TSSOP
* Fault Signal * Tight Tolerance Voltage Reference Over Line, Load, and Temperature
M16.15 M16.173 M16.15 M16.173
Applications
* Telecom and Datacom Power * Wireless Base Station Power * File Server Power * Industrial Power Systems * DC Transformers and Buss Regulators
Add -T suffix to part number for tape and reel packaging x= 0 1 CONTROL MODE Voltage Mode Current Mode
Pinout
ISL6740, ISL6741 (SOIC, TSSOP) TOP VIEW
OUTA 1 GND 2 SCSET 3 CT 4 SYNC 5 CS 6 VERROR 7 UV 8 16 OUTB 15 VREF 14 VDD 13 RTD 12 RTC 11 OTS 10 FAULT 9 SS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
ISL6740
V DD V REF SYNC
V REF 5.00 V 1% ENABLE
FL 100
Q T Q
OUTA
+ BG + GND
2
1.00 V UV IRTC R TC IRTD R TD SCSET CT CS V ERROR OTS
OUTB
4.5 k
PWM TOGGLE
SC S/D Internal OT Shutdown 130 - 150 C INHIBIT/V IN UV + INHIBIT EXT. SYNC N_SYNC OUT Bi-Directional Synchronization
S Q Q
OC S/D
V REF 70A
SYNC IN SS LOW
R
ON
SC LATCH
SS
ISL6740, ISL6741
SS DONE Oscillator 4.5 V CLK SS CLAMP + 300 k
OC LATCH
S R Q Q
15A
Short Circuit Detection
Q
SS HI
+ 4.25 V
SS DONE
Q
50 S RETRIGGERABLE ONE SHOT INHIBIT + OC DETECT
S R Q Q
SS LOW
+ -
0.27 V
FAULT LATCH SET DOMINANT
S R Q Q
0.6 V
FL
0.4
+ -
PWM COMPARATOR
PWM LATCH RESET DOMINANT
SC S/D OC S/D V REF + BG + -
FAULT
SS 0.4 0.5 V REF/2 V REF UV 4.65 V +
Functional Block Diagram (Continued)
ISL6741
V DD V REF SYNC
V REF 5.00 V 1% ENABLE
FL 100
Q T Q
OUTA
+ BG + GND
OUTB
4.5 k
PWM TOGGLE
3
UV IRTC R TC IRTD R TD SCSET CT CS V ERROR OTS
SC S/D Internal OT Shutdown 130 - 150 C INHIBIT/V IN UV 1.00 V + INHIBIT EXT. SYNC
R Q
V REF 70A
N_SYNC OUT Bi-Directional Synchronization SC LATCH SYNC IN
S Q
ON
SS
ISL6740, ISL6741
Oscillator 4.5 V CLK
+ 300 k
SS DONE
15A
SS CLAMP
Short Circuit Detection
SS DONE SS LOW + 0.27 V
INHIBIT + OC DETECT
S R Q Q
FAULT LATCH SET DOMINANT
S R Q Q
0.6 V
FL
80 m V + + 0.25
PWM COMPARATOR
PWM LATCH RESET DOMINANT SC S/D V REF SS 0.2 V REF/2 + V REF UV 4.65 V + BG + -
FAULT
Typical Application (ISL6740) - 48V Input DC Transformer, 12V @ 8A Output (ISL6740EVAL1)
SP1 VIN+ QR1 L1 C2 QH L3 T1 R8 C13 C9 C8 RTN C11 QR3 +12V
TP1
R10
L2
U3
VIN-
GND
VERROR
OUTB R17 R7 TP6 Q5 C15 R3 RTD OUTA V DD
VREF
UV
SCSET
SS
4
C1 T2 R9
R2 CR3
QL C14 R11
QR2
QR4
C12
C3 R1 C7 U1 HIP2101 C4 V DD HB HO HS C5 TP5 LO VSS LI HI TP4 CR1 R5
CR2 TP2 R14 R6 VREF C10 RT1
ISL6740, ISL6741
C18 R19 FAULT SYNC OTS
ISL6740
CS CT RTC
R13
C17 D1 R18 C6 R12 C16
R15
Typical Application (ISL6740) - 36 to 75 V Input, Regulated 12V @ 8A Output (ISL6740EVAL2)
SP1 VIN+ CR5 L1 C2 QH L3 T1 QR1 R26 C11 R8 QR3 + C9 L2 CR4 T2 CR6 R2 CR3 QL C14 QR2 R11 36-75V C12 C3 R1 C7 U1 HIP2101 C4 VDD HB HO HS C5 TP5 FAULT U3 SS SYNC OTS R19 LO VSS LI HI TP4 CR1 R5 R14 R6 VREF C10 RT1 + 12 V CR2 QR4 R27 R9 C8 RTN C21 +12V
C13
TP1
R10
C1
RTD
VREF
TP6 Q5 C15
UV
SCSET
5
VIN-
ISL6740, ISL6741
TP2
C18 R4
GND
VERROR
ISL6740
OUTB R17 R7 R3 OUTA VDD
CS CT RTC
R19
R20 R23 C22 C20
R25
R13
R21 U2 C17 D1 R18 C6 R12 C16 R15 D2 U4
C19
R24
Typical Application (ISL6741) - 48 to 5 Volt Push-Pull DC-DC Converter
+5 V +48V RTN
QR1 T1
R18
R19
R20
+
CR1
C9
EL7242
L1
+5 V
SS
RTD
UV
SCSET
VREF
6
C1 QR2 U5 Q1 RT1 Q2 R12 R11 SYNC R21 R2 R1 R3 VINGND OUTB OUTA R4 VDD FAULT OTS SYNC VERROR
CR2
T3 OUTB U3 CR3
ISL6740, ISL6741
OUTA CR4
ISL6741
CS CT RTC +5V
R14 R13 R6 R5 C8
R15
Q3 R7 R8
C3
C4
C5 R10 U2 C6 U4 R16 C7
VR1
C2 R9
R17
ISL6740, ISL6741
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V OUTA, OUTB, Signal Pins . . . . . . . . . . . . . . . . .GND - 0.3V to VREF VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A ESD Classification Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1500V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Thermal Information
Thermal Resistance Junction to Ambient (Typical) JA (oC/W) 16 Lead SOIC (Note 1) . . . . . . . . . . . . . . . . . . . . . . 77 16 Lead TSSOP (Note 1) . . . . . . . . . . . . . . . . . . . . . 102 Maximum Junction Temperature . . . . . . . . . . . . . . . -55oC to 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC, TSSOP- Lead Tips Only)
Operating Conditions
Temperature Range ISL6740Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 105oC ISL6741Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 105oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . 9VDC-16 VDC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. 9V < VDD < 20 V, RTD = 51.1k, RTC = 10k, CT = 470pF, TA = -40oC to 105oC (Note 4), Typical values are at TA = 25oC TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY VOLTAGE Start-Up Current, IDD Operating Current, IDD
VDD < START Threshold RLOAD, COUTA,B = 0 COUTA,B = 1nF
6.50 6.00 0.25
95 5.0 7.0 7.25 6.75 0.50
140 8.0 12.0 8.00 7.50 0.75
A mA mA V V V
UVLO START Threshold UVLO STOP Threshold Hysteresis REFERENCE VOLTAGE Overall Accuracy Long Term Stability Fault Voltage VREF Good Voltage Hysteresis Operational Current (source) Operational Current (sink) Current Limit CURRENT SENSE Current Limit Threshold CS to OUT Delay CS Sink Current Input Bias Current CS to PWM Comparator Input Offset (ISL6741) Gain (ISL6741) (Note 4) ACS = VERROR/VCS (Note 4) VERROR = VREF IVREF = 0, -20mA TA = 125oC, 1000 hours (Note 4)
4.900 4.10 4.25 75 -20 5 -25
5.000 3 4.55 4.75 165 -
5.050 4.75 VREF -.05 250 -100
V mV V V mV mA mA mA
0.55 -1.00 -
0.6 35 10 80 4
0.65 50 1.00 -
V ns mA A mV V/V
7
ISL6740, ISL6741
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. 9V < VDD < 20 V, RTD = 51.1k, RTC = 10k, CT = 470pF, TA = -40oC to 105oC (Note 4), Typical values are at TA = 25oC (Continued) TEST CONDITIONS MIN 1 TYP 10 MAX UNITS M %
PARAMETER SCSET Input Impedance SC Setpoint Accuracy PULSE WIDTH MODULATOR VERROR Input Impedance Minimum Duty Cycle
400 VERROR < CS Offset (ISL6741) VERROR < CT Valley Voltage (ISL6740) 0.4 -
83 1.0 0.25 0.4 0.4 0.5 0.2
0 0 1.25 -
k % % % V
Maximum Duty Cycle VERROR to PWM Comparator Input Offset (ISL6741) VERROR to PWM Comparator Input Gain (ISL6741) VERROR to PWM Comparator Input Gain (ISL6740) CT to PWM Comparator Input Gain (ISL6740) SS to PWM Comparator Input Gain (ISL6740) SS to PWM Comparator Input Gain (ISL6741) OSCILLATOR Frequency Accuracy Frequency Variation with VDD
VERROR > 4.75V (Note 6) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4)
V/V V/V V/V V/V
TA = 25oC T = 105oC (F20V- - F9V)/F9V T = -40oC (F20V- - F9V)/F9V
333 1.88 45 0.75 2.70
351 2 2 8 2.0 55 0.80 2.80 2.000
369 3 3 2.12 65 0.85 2.90 -
kHz % % % A/A A/A V V V
Temperature Stability Charge Current Gain Discharge Current Gain CT Valley Voltage CT Peak Voltage RTD, RTC Voltage SYNCHRONIZATION Input High Threshold (VIH), Minimum Input Low Threshold (VIL), Maximum Input Impedance Input Frequency Range
(Note 4)
RLOAD = 0
-
4.0 -
4.5
0.8 Free Running 100 400 -
V V k Hz
(Note 4)
0.6x Free Running -10 250 -
-
High Level Output Voltage (VOH) Low Level Output Voltage (VOL) SYNC Output Current SYNC Output Pulse Duration (minimum) SYNC Advance
ILOAD = -1mA ILOAD = 10A VOH > 2.0V (Note 4) (Notes 4, 5) SYNC rising edge to GATE falling edge, CGATE = CSYNC = 100pF (Note 4)
4.5 5
V mV mA ns ns
SOFTSTART Charging Current SS Clamp Voltage SS = 2V -45 4.35 -55 4.5 -75 4.65 A V
8
ISL6740, ISL6741
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. 9V < VDD < 20 V, RTD = 51.1k, RTC = 10k, CT = 470pF, TA = -40oC to 105oC (Note 4), Typical values are at TA = 25oC (Continued) TEST CONDITIONS MIN 0.20 13 0.25 TYP 0.25 18 10.0 0.27 MAX 0.30 23 0.33 UNITS V A mA V
PARAMETER
Sustained Over Current Threshold Voltage (ISL6740) Charged Threshold minus: Over Current/Short Circuit Discharge Current Fault SS Discharge Current Reset Threshold Voltage FAULT Fault High Level Output Voltage (VOH) Fault Low Level Output Voltage (VOL) Fault Rise Time Fault Fall Time OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Rise Time Fall Time THERMAL PROTECTION Thermal Shutdown Thermal Shutdown Clear Hysteresis, Internal Protection Reference, External Protection Hysteresis, External Protection SUPPLY UVLO/INHIBIT Input Voltage Low/Inhibit Threshold Hysteresis, Switched Current Amplitude Input High Clamp Voltage Input Impedance NOTES: 3. Specifications at -40oC and 105o C are guaranteed by design, not production tested. 4. Guaranteed by design, not 100% tested in production. 5. SYNC pulse width is the greater of this value or the CT discharge time. (Note 4) (Note 4) (Note 4) VREF - OUTA or OUTB, IOUT = -50mA OUTA or OUTB - GND, IOUT = 50mA CGATE = 1nF, VDD = 15V (Note 4) CGATE = 1nF, VDD = 15V (Note 4) ILOAD = -10mA ILOAD = 10mA CLOAD = 100pF (Note 4) CLOAD = 100pF (Note 4) SS = 2V SS = 2V
2.85 -
3.5 0.4 15 15
0.9 -
V V ns ns
-
0.5 0.5 50 40
1.0 1.0 100 80
V V ns ns
135 120 2.375 18
145 130 15 2.50 25
155 140 2.625 30
oC oC oC
V A
0.97 7 4.8 1
1.00 10 -
1.03 15 -
V A V M
6. This is the maximum duty cycle achievable using the specified values of RTC, RTD, and CT. Larger or smaller maximum duty cycles may be obtained using other values for these components. See Equations 2-4.
9
ISL6740, ISL6741 Typical Performance Curves
1.001 CT DISCHARGE CURRENT GAIN -25 -10 5 20 35 50 65 80 95 110
65
NORMALIZED VREF
1
60
55
0.999
50
0.998
45
0.997 -40
40
0
50
100 150 200 250 300 350 400 450 RTD CURRENT (A)
500
TEMPERATURE (C)
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. OSCILLATOR CT DISCHARGE CURRENT GAIN
1*104
DEADTIME - TD (ns)
FREQUENCY (Hz)
CT (pF) = 1000 680 470 1*103 330 220 100
1*106
1*105 RTD = 10K CT (pF) = 100 220 330 470 1*104 10 20 30
100
680 1000 40 50 60 70 80 90 100
10 10
20
30
40
50
60
70
80
90
100
RTD (k)
RTC (k)
FIGURE 3. DEADTIME (TD) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. The total supply current, IDD, will be dependent on the load applied to outputs OUTA and OUTB. Total IDD current is the sum of the quiescent current and the average output current. Knowing the operating frequency, Fsw, and the output loading capacitance charge, Q, per output, the average output current can be calculated from:
I OUT = 2 * Q * F SW A (EQ. 1)
RTC - This is the oscillator timing capacitor charge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the charge current. The charge current is nominally twice this current. The PWM maximum ON time is determined by the timing capacitor charge duration. RTD - This is the oscillator timing capacitor discharge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the discharge current. The discharge current is nominally 50x this current. The PWM deadtime is determined by the timing capacitor discharge duration. CT - The oscillator timing capacitor is connected between this pin and GND. VERROR - The inverting input of the PWM comparator. The error voltage is applied to this pin to control the duty cycle. Increasing the signal level increases the duty cycle. The node may be driven with an external error amplifier or optocoupler.
SYNC - A bidirectional synchronization signal used to coordinate the switching frequency of multiple units. Synchronization may be achieved by connecting the SYNC signal of each unit together or by using an external master clock signal. The oscillator timing capacitor, CT, is always required regardless of the synchronization method used. The paralleled unit with the highest oscillator frequency assumes control. 10
ISL6740, ISL6741
The ISL6740, ISL6741 features a built-in soft start. Soft start is implemented as a clamp on the error voltage input. OTS - The non-inverting input to the over temperature shutdown comparator. The signal input at this pin is compared to an internal threshold of VREF/2. If the voltage at this pin exceeds the threshold, the Fault signal is asserted and the outputs are disabled until the condition clears. There is a nominal 25A switched current source used for hysteresis. The amount of hysteresis is adjustable by varying the source impedance of the signal into this pin. OTS may be used to monitor parameters other than temperature, such as voltage. Any signal for which a high out-of-bounds monitor is desired may utilize the OTS comparator. FAULT - The Fault signal is asserted high whenever the outputs, OUTA and OUTB, are disabled. This occurs during an over temperature fault, an input UV fault, a VREF UV fault, or during an over current (ISL6740) or short circuit shutdown fault. Fault can be used to disable synchronous rectifiers whenever the outputs are disabled. Fault is a three-state output and is high impedance during the soft start cycle. Adding a pull-up resistor to VREF or a pull-down resistor to ground determines the state of Fault during soft start. This feature allows the designer to use the Fault signal to enable or disable output synchronous rectifiers during soft start. UV - Undervoltage monitor input pin. A resistor divider between the input source voltage and GND sets the under voltage lock out threshold. The signal is compared to an internal 1.00V reference to detect an under voltage or inhibit condition. CS - This is the input to the current sense comparator(s). The IC has the PWM comparator for peak current mode control (ISL6741) and an over current protection comparator. The over current comparator threshold is set at 0.600V nominal. The CS pin is shorted to GND at the end of each switching cycle. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. This delay may allow an overlap such that the CS signal may be discharged while the current signal is still active. If the current sense source is low impedance it will cause increased power dissipation. ISL6740 - Exceeding the over-current threshold will start a delayed shutdown sequence. Once an over current condition is detected, the soft start charge current source is disabled. The soft start capacitor begins discharging through a 25A current source, and if it discharges to less than 4.25V (Sustained Over Current Threshold), a shutdown condition occurs and the OUTA and OUTB outputs are forced low. When the soft start voltage reaches 0.27V (Reset Threshold) a soft start cycle begins. An over current condition must be absent for 50s before the delayed shutdown control resets. If the over current condition ceases, and an additional 50s period elapses before the shutdown threshold is reached, no shutdown occurs. The SS charging current is re-enabled and the soft start voltage is allowed to recover. ISL6741 - The ISL6741 current mode controller does not shutdown due to an overcurrent condition. The pulse-bypulse current limit characteristic of peak current mode control limits the output current to acceptable levels. GND - Reference and power ground for all functions on this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. OUTA and OUTB - Alternate half cycle output stages. Each output is capable of 0.5A peak currents for driving logic level power MOSFETs or MOSFET drivers. Each output provides very low impedance to overshoot and undershoot. VREF - The 5.00V reference voltage output. +1/-2% tolerance over line, load and operating temperature. Bypass to GND with a 0.047F to 2.2F ceramic capacitor. Capacitors outside of this range may cause oscillation. SS - Connect the soft start timing capacitor between this pin and GND to control the duration of soft start. The value of the capacitor determines the rate of increase of the duty cycle during start up, controls the over current shutdown delay (ISL6740), and the over current and short circuit hiccup restart period. SCSET - Sets the duty cycle threshold that corresponds to a short circuit condition. A resistive divider between RTC and GND or RTD and GND, or a voltage between 0 and 2V may be used to adjust the SCSET threshold. If using a resistor divider from either RTC or RTD, the impedance to GND affects the oscillator timing and should be considered when determining the oscillator timing components. Connecting SCSET to GND disables short circuit shutdown and hiccup.
Functional Description
Features
The ISL6740, ISL6741 PWMs are an excellent choice for low cost bridge and push-pull topologies for applications requiring accurate duty cycle and deadtime control. With its many protection and control features, a highly flexible design with minimal external components is possible. Among its many features are current mode control (ISL6741), adjustable soft start, over current protection, thermal protection, bidirectional synchronization, fault indication, and adjustable frequency.
11
ISL6740, ISL6741
Oscillator
The ISL6740, ISL6741 have an oscillator with a programmable frequency range to 2MHz, which can be programmed with two resistors and capacitor. The use of three timing elements, RTC, RTD, and CT allow great flexibility and precision when setting the oscillator frequency. The switching period may be considered the sum of the timing capacitor charge and discharge durations. The charge duration is determined by RTC and CT. The discharge duration is determined by RTD and CT.
T C 0.5 * R TC * C T T D 0.02 * R TD * C T 1 T SW = T C + T D = ----------F SW S (EQ. 2)
being prematurely terminated by the external SYNC pulse. Consequently, the timing capacitor is not fully charged when the discharge cycle begins. This effect is only a concern when an external master clock is used, or if units with different operating frequencies are paralleled.
Soft Start Operation
The ISL6740, ISL6741 feature a soft start using an external capacitor in conjunction with an internal current source. Soft start reduces stresses and surge currents during start up. Upon start up, the soft start circuitry clamps the error voltage input (VERROR pin) indirectly to a value equal to the soft start voltage. The soft start clamp does not actually clamp the error voltage input as is done in many implementations. Rather the PWM comparator has two inverting inputs such that the lower voltage is in control. The output pulse width increases as the soft start capacitor voltage increases. This has the effect of increasing the duty cycle from zero to the regulation pulse width during the soft start period. When the soft start voltage exceeds the error voltage, soft start is completed. Soft start occurs during start-up, after recovery from a Fault condition or over current/short circuit shutdown. The soft start voltage is clamped to 4.5V. The Fault signal output is high impedance during the soft start cycle. A pull-up resistor to VREF or a pull-down resistor to ground should be added to achieve the desired state of Fault during soft start.
S
(EQ. 3) (EQ. 4)
S
where TC and TD are the charge and discharge times, respectively, TSW is the oscillator free running period, and f is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. This delay ads directly to the switching duration, but also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very low charge and discharge currents are used, there will be increased error due to the input impedance at the CT pin. The maximum duty cycle, D, and percent deadtime, DT, can be calculated from:
TC D = ----------T SW DT = 1 - D (EQ. 5)
Gate Drive
The ISL6740, ISL6741 are capable of sourcing and sinking 0.5A peak current, but are primarily intended to be used in conjunction with a MOSFET driver due to the 5V drive level. To limit the peak current through the IC, an external resistor may be placed between the totem-pole output of the IC (OUTA or OUTB pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
(EQ. 6)
Implementing Synchronization
The oscillator can be synchronized to an external clock applied to the SYNC pin or by connecting the SYNC pins of multiple ICs together. If an external master clock signal is used, the free running frequency of the oscillator should be ~10% slower than the desired synchronous frequency. The external master clock signal should have a pulse width greater than 20ns. The SYNC circuitry will not respond to an external signal during the first 60% of the oscillator switching cycle. The SYNC input is edge triggered and its duration does not affect oscillator operation. However, the deadtime is affected by the SYNC frequency. A higher frequency signal applied to the SYNC input will shorten the deadtime. The shortened deadtime is the result of the timing capacitor charge cycle
Under Voltage Monitor and Inhibit
The UV input is used for input source under voltage lockout and inhibit functions. If the node voltage falls below 1.00V a UV shutdown fault occurs. This may be caused by low source voltage or by intentional grounding of the pin to disable the outputs. There is a nominal 10A switched current source used to create hysteresis. The current source is active only during an UV/Inhibit fault; otherwise, it is inactive and does not affect the node voltage. The magnitude of the hysteresis is a function of the external resistor divider impedance. If the resistor divider impedance results in too little hysteresis, a series resistor between the UV pin and the divider may be used to increase the hysteresis. A soft start cycle begins when the UV/Inhibit fault clears.
12
ISL6740, ISL6741
The voltage hysteresis created by the switched current source and the external impedance is generally small due to the large resistor divider ratio required to scale the input voltage down to the UV threshold level. A small capacitor placed between the UV input and ground may be required to filter noise out. The duration of the OC shutdown period can be increased by adding a resistor between VREF and SS. The value of the resistor must be large enough so that the minimum specified SS discharge current is not exceeded. Using a 422k resistor, for example, will result in a small current being injected into SS, effectively reducing the discharge current. This will increase the OFF time by about 60%, nominally. The external pull-up resistor will also decrease the SS duration, so its effect should be considered when selecting the value of the SS capacitor. Latching OC shutdown is also possible by using a lower valued resistor between VREF and SS. If the SS node is not allowed to discharge below the SS reset threshold, the IC will not recover from an over-current fault. The value of the resistor must be low enough so that the maximum specified discharge current is not sufficient to pull SS below 0.33V. A 200k resistor, for example, prevents SS from discharging below ~0.4V. Again, the external pull-up resistor will decrease the SS duration, so its effect should be considered when selecting the value of the SS capacitor. ISL6741 - Over current results in pulse-by-pulse duty cycle reduction as occurs in any peak current mode controller. This results in a well controlled decrease in output voltage with increasing current beyond the over current threshold. An over current condition in the ISL6741 will not cause a shutdown.
VIN
R1 1.00V R3 R2 10A ON + -
FIGURE 5. UV HYSTERESIS
As VIN decreases to a UV condition, the threshold level is:
R1 + R2 V IN ( DOWN ) = --------------------R2 V (EQ. 7)
The hysteresis voltage, V, is:
V = 10
-5
R1 + R2 * R1 + R3 * --------------------- R2
Short Circuit Operation
V (EQ. 8)
Setting R3 equal to zero results in the minimum hysteresis, and yields:
V = 10
-5
* R1
V
(EQ. 9)
As VIN increases from a UV condition, the threshold level is:
V IN ( UP ) = V IN ( DOWN ) + V V (EQ. 10)
Over Current Operation
ISL6740 - Over current delayed shutdown is enabled once the soft start cycle is complete. If an over current condition is detected, the soft start charging current source is disabled and the soft start capacitor is allowed to discharge through a 15A source. At the same time a 50s re-triggerable oneshot timer is activated. It remains active for 50s after the over current condition ceases. If the soft start capacitor discharges by more then 0.25V to 4.25V, the output is disabled and the Fault signal asserted. This state continues until the soft start voltage reaches 270mV, at which time a new soft start cycle is initiated. If the over current condition stops at least 50s prior to the soft start voltage reaching 4.25V, the soft start charging currents revert to normal operation and the soft start voltage is allowed to recover.
A short circuit condition is defined as the simultaneous occurrence of current limit and a reduced duty cycle. The degree of reduced duty cycle is user adjustable using the SCSET input. A resistor divider between either RTD or RTC and GND to RCSET sets a threshold that is compared to the voltage on the timing capacitor, CT. The resistor divider percentage corresponds to the fraction of the maximum duty cycle below which a short circuit may exist. If the timing capacitor voltage fails to exceed the threshold before an over current pulse is detected, a short circuit condition exists. A shutdown and soft start cycle will begin if 8 short circuit events occur within 32 oscillator cycles. Connecting SCSET to GND disables this feature. Since the current sourced from both RTC and RTD determine the charge and discharge currents for the timing capacitor, the effect of the SCSET divider must be included in the timing calculations. Typically the resistor between RTC and GND is formed by two series resistors with the center node connected to SCSET. Alternatively, SCSET may be set using a voltage between 0V and 2V. This voltage divided by 2 determines the percentage of the maximum duty cycle that corresponds to a short circuit when current limit is active. For example, if the maximum duty cycle is 95% and 1V is applied to SCSET, then the short circuit duty cycle is 50% of 95% or 47.5%.
13
ISL6740, ISL6741
Fault Conditions
A fault condition occurs if VREF falls below 4.65V, the UV input falls below 1.00V, the thermal protection is triggered, or if OTS faults. When a fault is detected, OUTA and OUTB outputs are disabled, the Fault signal is asserted, and the soft start capacitor is quickly discharged. When the fault condition clears and the soft start voltage is below the reset threshold, a soft start cycle begins. The Fault signal is high impedance during the soft start cycle. An over current condition that results in shutdown (ISL6740), or a short circuit shutdown also cause assertion of the Fault signal. The difference between a current fault and the faults described earlier is that the soft start capacitor is not quickly discharged. The initiation of a new soft start cycle is delayed while the soft start capacitor is discharged at a 15A rate. This keeps the average output current to a minimum. If a PTC is desired, then position R2 may be substituted. The threshold with increasing temperature is set by making the fixed resistance equal in value to the thermistor resistance at the desired trip temperature. VTH = 2.5V and R1 = R2 (HOT) To determine the value of the hysteresis resistor, R3, select the value of thermistor resistance that corresponds to the desired reset temperature.
10 * ( R1 - R2 ) - R1 * R2 R3 = --------------------------------------------------------------------R1 + R2
5
(EQ. 11)
If the hysteresis resistor, R3, is not desired, the value of the thermistor resistance at the reset temperature can be determined from:
2.5 * R2 R1 = ----------------------------------------5 2.5 - 10 * R2 2.5 * R1 R2 = ----------------------------------------5 2.5 + 10 * R1 ( NTC ) (EQ. 12)
Thermal Protection
Two methods of over temperature protection are provided. The first method is an on board temperature sensor that protects the device should the junction temperature exceed 145C. There is approximately 15C of hysteresis. The second method uses an internal comparator with a 2.5V reference (VREF/2). The non-inverting input to the comparator is accessible through the OTS pin. A thermistor or thermal sensor located at or near the area of interest may be connected to this input. There is a nominal 25A switched current source used to create hysteresis. The current source is active only during an OT fault; otherwise, it is inactive and does not affect the node voltage. The magnitude of the hysteresis is a function of the external resistor divider impedance. Either a positive temperature coefficient (PTC) or a negative temperature coefficient (NTC) thermistor may be used. If a NTC is desired, position R1 may be substituted.
( PTC )
(EQ. 13)
The OTS comparator may also be used to monitor signals other than suggested above. It may also be used to monitor any voltage signal for which an excess requires a response as described above. Input or output voltage monitoring are examples of this.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. VDD should be bypassed directly to GND with good high frequency capacitance.
Typical Application
The Typical Application Schematic features the ISL6740 in an unregulated half-bridge DC-DC converter configuration, often referred to as a DC Transformer or Bus Regulator. The ISL6740EVAL1 demonstration unit implements this design and is available for evaluation.
VREF VREF ON R1 25A VREF/2 + -
R3 R2
The input voltage range is 48 10%V DC. The output is a nominal 12V when the input voltage is at 48V. Since this is an unregulated topology, the output voltage will vary proportionately with input voltage. The load regulation is a function of resistance between the source and the converter output. The output is rated at 8A.
FIGURE 6. OTS HYSTERESIS
14
ISL6740, ISL6741
Circuit Element Descriptions
The converter design may be broken down into the following functional blocks: Input Filtering: L1, C1, R1 Half-Bridge Capacitors: C2, C3 Isolation Transformer: T1 Primary Snubber: C13, R10 Start Bias Regulator: CR3, R2, R7, C6, Q5, D1 Supply Bypass Components: R3, C15, C4, C5 Main MOSFET Power Switch: QH, QL Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10, C14 Control Circuit: U3, RT1, R14, R19, R13, R15, R17, R18, C16, C18, C17 Output Rectification and Filtering: QR1, QR2, QR3, QR4, L2, C9, C8 Secondary Snubber: R8, R9, C11, C12 FET Driver: U1 ZVS Resonant Delay (Optional): L3, C7
nS nP nS nSR
energy, the number of turns that have to be wound, and the wire gauge needed. Often the window area (the space used for the windings) and power loss determine the final core size. * Determine maximum desired flux density. Depending on the frequency of operation, the core material selected, and the operating environment, the allowed flux density must be determined. The decision of what flux density to allow is often difficult to determine initially. Usually the highest flux density that produces an acceptable design is used, but often the winding geometry dictates a larger core than is indicated based on flux density alone. * Determine the number of primary turns. * Select the wire gauge for each winding. * Determine winding order and insulation requirements. * Verify the design.
nSR
Design Criteria
The following design requirements were selected: Switching Frequency, Fsw: 235kHz VIN: 48 10%V VOUT: 12V (nominal) @ IOUT = 8A POUT: 100W Efficiency: 95% Ripple: 1%
FIGURE 7. TRANSFORMER SCHEMATIC
For this application we have selected a planar structure to achieve a low profile design. A PQ style core was selected because of its round center leg cross section, but there are many suitable core styles available. Since the converter is operating open loop at nearly 100% duty cycle, the turns ratio, N, is simply the ratio of the input voltage to the output voltage divided by 2.
V IN 48 N = ------------------------ = -------------- = 2 V OUT * 2 12 * 2 (EQ. 14)
Transformer Design
The design of a transformer for a half-bridge application is a straight forward affair, although iterative. It is a process of many compromises, and even experienced designers will produce different designs when presented with identical requirements. The iterative design process is not presented here for clarity. The abbreviated design process follows: * Select a core geometry suitable for the application. Constraints of height, footprint, mounting preference, and operating environment will affect the choice. * Determine the turns ratio. * Select suitable core material(s). * Select maximum flux density desired for operation. * Select core size. Core size will be dictated by the capability of the core structure to store the required
The factor of 2 divisor is due to the half-bridge topology. Only half of the input voltage is applied to the primary of the transformer. A PC44HPQ20/6 "E-Core" plus a PC44PQ20/3 "I-Core" from TDK were selected for the transformer core. The ferrite material is PC44. The core parameter of concern for flux density is the effective core cross sectional area, Ae. For the PQ core pieces selected: Ae = 0.62cm2 or 6.2e -5m2 Using Faraday's Law, V = N d/dt, the number of primary turns can be determined once the maximum flux density is set. An acceptable Bmax is ultimately determined by the
15
ISL6740, ISL6741
allowable power dissipation in the ferrite material and is influenced by the lossiness of the core, core geometry, operating ambient temperature, and air flow. The TDK datasheet for PC44 material indicates a core loss factor of ~400 mW/cm3 with a 2000 gauss 100kHz sinusoidal excitation. The application uses a 235kHz square wave excitation, so no direct comparison between the application and the data can be made. Interpolation of the data is required. The core volume is approximately 1.6cm3, so the estimated core loss is
f act 3 mW 200kHz P loss ---------- * cm * --------------- = 0.4 * 1.6 * -------------------- = 1.28 3 f meas 100kHz cm W (EQ. 15)
yields 555mils2 (0.785 sq. mils/c.m.). Dividing by the trace width results in a copper thickness of 4.44mils (0.112mm). Using 1.3mils/oz. of copper requires a copper weight of 3.4oz. For reasons of cost, 3oz. copper was selected. One layer of each secondary winding also contains the synchronous rectifier winding. For this layer the secondary trace width is reduced by 0.025 inches to 0.100 inches(0.015 inches for the SR winding trace width and 0.010 inches spacing between the SR winding and the secondary winding). The choice of copper weight may be validated by calculating the DC copper losses of the secondary winding as follows. Ignoring the terminal and lead-in resistance, the resistance of each layer of the secondary may be approximated using EQ. 18.
2 R = ---------------------- r 2 t * ln ---- r 1 (EQ. 18)
1.28W of dissipation is significant for a core of this size. Reducing the flux density to 1200 gauss will reduce the dissipation by about the same percentage, or 40%. Ultimately, evaluation of the transformer's performance in the application will determine what is acceptable. From Faraday's Law and using 1200 gauss peak flux density (B = 2400 gauss or 0.24 tesla)
-6 V IN * T ON 53 * 2 * 10 N = ----------------------------- = ---------------------------------------------------- = 3.56 -5 2 * A e * B 2 * 6.2 * 10 * 0.24
where R = Winding resistance
turns (EQ. 16)
= Resistivity of copper = 669e-9-inches at 20C t = Thickness of the copper (3 oz.) = 3.9e-3 inches
Rounding up yields 4 turns for the primary winding. The peak flux density using 4 turns is ~1100 gauss. From EQ. 1, the number of secondary turns is 2. The volts/turn for this design ranges from 5.4V at VIN = 43V to 6.6V at VIN = 53V. Therefore, the synchronous rectifier (SR) windings may be set at 1 turn each with proper FET selection. Selecting 2 turns for the synchronous rectifier windings would also be acceptable, but the gate drive losses would increase. The next step is to determine the equivalent wire gauge for the planar structure. Since each secondary winding conducts for only 50% of the period, the RMS current is
I RMS = I OUT * D = 10 * 0.5 = 7.07 A (EQ. 17)
r2 = Outside radius of the copper trace = 0.324 or 0.299 inches r1 = Inside radius of the copper trace = 0.199 inches The winding without the SR winding on the same layer has a DC resistance 2.21m. The winding that shares the layer with the SR winding has a DC resistance of 2.65m. With the secondary configured as a 4 turn center tapped winding (2 turns each side of the tap), the total DC power loss for the secondary at 20C is 486mW. The primary windings have an RMS current of approximately 5 A (IOUT x NS/NP at ~ 100% duty cycle). The primary is configured as 2 layers, 2 turns per layer to minimize the winding stack height. Allowing 0.020 inches edge clearance and 0.010 inches between turns yields a trace width of 0.0575 inches. Ignoring the terminal and lead-in resistance, and using EQ. 18, the inner trace has a resistance of 4.25m, and the outer trace has a resistance of 5.52m. The resistance of the primary then is 19.5m at 20C. The total DC power loss for the secondary at 20C is 489mW. Improved efficiency and thermal performance could be achieved by selecting heavier copper weight for the windings. Evaluation in the application will determine its need.
where D is the duty cycle. Since an FR-4 PWB planar winding structure was selected, the width of the copper traces is limited by the window area width, and the number of layers is limited by the window area height. The PQ core selected has a usable window area width of 0.165 inches. Allowing one turn per layer and 0.020 inches clearance at the edges allows a maximum trace width of 0.125 inches. Using 100 circular mils(c.m.)/A as a guideline for current density, and from EQ. 17, 707c.m. are required for each of the secondary windings (a circular mil is the area of a circle 0.001 inches in diameter). Converting c.m. to square mils
16
ISL6740, ISL6741
The order and geometry of the windings affects the AC resistance, winding capacitance, and leakage inductance of the finished transformer. To mitigate these effects, interleaving the windings is necessary. The primary winding is sandwiched between the two secondary windings. The winding layout appears below.
FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING
FIGURE 7A. TOP LAYER: 1 TURN SECONDARY AND SR WINDINGS
FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING
FIGURE 7B. INT. LAYER 1: 1 TURN SECONDARY WINDING
FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR WINDINGS
0.689 0.358 0.807 0.639
FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING
0.403
0.169 0.000 0.000 0.184 0.479 0.774 1.054
FIGURE 7G. PWB DIMENSIONS
17
ISL6740, ISL6741
MOSFET Selection
The criteria for selection of the primary side half-bridge FETs and the secondary side synchronous rectifier FETs is largely based on the current and voltage rating of the device. However, the FET drain-source capacitance and gate charge cannot be ignored. The zero voltage switch (ZVS) transition timing is dependent on the transformer's leakage inductance and the capacitance at the node between the upper FET source and the lower FET drain. The node capacitance is comprised of the drain-source capacitance of the FETs and the transformer parasitic capacitance. The leakage inductance and capacitance form an LC resonant tank circuit which determines the duration of the transition. The amount of energy stored in the LC tank circuit determines the transition voltage amplitude. If the leakage inductance energy is too low, ZVS operation is not possible and near or partial ZVS operation occurs. As the leakage energy increases, the voltage amplitude increases until it is clamped by the FET body diode to ground or VIN, depending on which FET conducts. When the leakage energy exceeds the minimum required for ZVS operation, the voltage is clamped until the energy is transferred. This behavior increases the time window for ZVS operation. This behavior is not without consequences, however. The transition time and the period of time during which the voltage is clamped reduces the effective duty cycle. The gate charge affects the switching speed of the FETs. Higher gate charge translates into higher drive requirements and/or slower switching speeds. The energy required to drive the gates is dissipated as heat. The maximum input voltage, VIN, plus transient voltage, determines the voltage rating required. With a maximum input voltage of 53V for this application, and if we allow a 10% adder for transients, a voltage rating of 60V or higher will suffice. The RMS current through the each primary side FET can be determined from EQ. 17, substituting 5A of primary current for IOUT. The result is 3.5A RMS. Fairchild FDS3672 FETs, rated at 100V and 7.5A (rDS(ON) = 22m), were selected for the half-bridge switches. The synchronous rectifier FETs must withstand approximately one half of the input voltage assuming no switching transients are present. This suggests a device capable of withstanding at least 30V is required. Empirical testing in the circuit revealed switching transients of 20V were present across the device indicating a rating of at least 60V is required. The RMS current rating of 7.07A for each SR FET requires a low rDS(ON) to minimize conduction losses, which is difficult to find in a 60V device. It was decided to use two devices in parallel to simplify the thermal design. Two Fairchild FDS5670 devices are used in parallel for a total of four SR FETs. The FDS5670 is rated at 60V and 10A (rDS(ON) = 14m).
Oscillator Component Selection
The desired operating frequency of 235kHz for the converter was established in the Design Criteria section. The oscillator frequency operates at twice the frequency of the converter because two clock cycles are required for a complete converter period. During each oscillator cycle the timing capacitor, CT, must be charged and discharged. Determining the required discharge time to achieve zero voltage switching (ZVS) is the critical design goal in selecting the timing components. The discharge time sets the deadtime between the two outputs, and is the same as ZVS transition time. Once the discharge time is determined, the remainder of the period becomes the charge time. The ZVS transition duration is determined by the transformer's primary leakage inductance, Llk, by the FET Coss, by the transformer's parasitic winding capacitance, and by any other parasitic elements on the node. The parameters may be determined by measurement, calculation, estimate, or by some combination of these methods.
L lk * ( 2C oss + C xfrmr ) t zvs ------------------------------------------------------------------2 S (EQ. 19)
Device output capacitance, Coss, is non-linear with applied voltage. To find the equivalent discrete capacitance, Cfet, a charge model is used. Using a known current source, the time required to charge the MOSFET drain to the desired operating voltage is determined and the equivalent capacitance is calculated.
Ichg * t Cfet = ------------------V F (EQ. 20)
Once the estimated transition time is determined, it must be verified directly in the application. The transformer leakage inductance was measured at 125nH and the combined capacitance was estimated at 2000pF. Calculations indicate a transition period of ~ 25ns. Verification of the performance yielded a value of TD closer to 45ns. The remainder of the switching half-period is the charge time, TC, and can be found from
-9 1 1 T C = --------------- - T D = --------------------------------- - 45 * 10 = 2.08 3 2 * FS 2 * 235 * 10
s (EQ. 21)
where FS is the converter switching frequency. Using Fig. 4, the capacitor value appropriate to the desired oscillator operating frequency of 470kHz can be selected. A CT value of 100pF, 220pF, or 330pF is appropriate for this frequency. A value of 220pF was selected.
18
ISL6740, ISL6741
To obtain the proper value for RTD, EQ. 3 is used. Since there is a 10ns propagation delay in the oscillator circuit, it must be included in the calculation. The value of RTD selected is 8.06k. A similar procedure is used to determine the value of RTC using EQ. 2. The value of RTC selected is the series combination of 17.4k and 1.27k. See section Over Current Component Selection for further explanation. ripple current under steady state operation increases significantly as the duty cycle decreases.
14 13 12 11 10 9 8 0.9950 V (L1:1) I (L1)
Output Filter Design
The output filter inductor and capacitor selection is simple and straightforward. Under steady state operating conditions the voltage across the inductor is very small due to the large duty cycle. Voltage is applied across the inductor only during the switch transition time, about 45ns in this application. Ignoring the voltage drop across the SR FETs, the voltage across the inductor during the ON time with VIN = 48V is
V IN * N S * ( 1 - D ) V L = V S - V OUT = ----------------------------------------------- 250 2N P mV (EQ. 22)
15 V (L1:1) I (L1)
0.9960
0.9970
0.9980 TIME (ms)
0.9990
1.000
FIGURE 8. STEADY STATE SECONDARY WINDING VOLTAGE AND INDUCTOR CURRENT
where VL is the inductor voltage VS is the voltage across the secondary winding VOUT is the output voltage If we allow a current ramp, I, of 5% of the rated output current, the minimum inductance required is
V L * T ON 0.25 * 2.08 L ------------------------ = ---------------------------- = 1.04 I 0.5 H (EQ. 23)
10
5 0.986
0.988
0.990
0.992
0.994
0.996
0.998
1.000
An inductor value of 1.4H, rated for 18A was selected. With a maximum input voltage of 53V, the maximum output voltage is about 13V. The closest higher voltage rated capacitor is 16V. Under steady state operating conditions the ripple current in the capacitor is small, so it would seem appropriate to have a low ripple current rated capacitor. However, a high rated ripple current capacitor was selected based on the nature of the intended load, multiple buck regulators. To minimize the output impedance of the filter, a Sanyo OSCON 16SH150M capacitor in parallel with a 22F ceramic capacitor were selected.
TIME (ms)
FIGURE 9. SECONDARY WINDING VOLTAGE AND INDUCTOR CURRENT DURING CURRENT LIMIT OPERATION
Over Current Component Selection
There are two circuit areas to consider when selecting the components for over current protection, current limit and short circuit shutdown. The current limit threshold is fixed at 0.6V while the short circuit threshold is set to a fraction of the duty cycle the designer wishes to define as a short circuit. The current level that corresponds to the over current threshold must be chosen to allow for the dynamic behavior of an open loop converter. In particular, the low inductor
Figures 8 and 9 show the behavior of the inductor ripple under steady state and over current conditions. In this example, the peak current limit is set at 11A. The peak current limit causes the duty cycle to decrease resulting in a reduction of the average current through the inductor. The implication is that the converter can not supply the same output current in current limit that it can supply under steady state conditions. The peak current limit setpoint must take this behavior into consideration. A 3.32 current sense resistor was selected for the rectified secondary of current transformer T2, corresponding to a peak current limit setpoint of 16.5A. The short circuit protection involves setting a voltage between 0 and 2V on the SCSET pin. The applied voltage divided by 2 is the percent of maximum duty cycle that corresponds to a short circuit when the peak current limit is active. A divider from RTC to ground provides an easy method to achieve this. The divider between RTC and GND
19
ISL6740, ISL6741
formed by R13 and R15 determines the percent of maximum duty cycle that corresponds to a short circuit. The divider ratio formed by R13 and R15 is
R13 1.27k ---------------------------- = ----------------------------------- = 0.068 R13 + R15 1.27k + 17.4k (EQ. 24)
regulation is not required, such as those application that use downstream DC-DC converters, this design approach is viable.
Waveforms
Typical waveforms can be found in the following Figures. Figure 13 shows the output voltage during start up.
Therefore, the duty cycle that corresponds to a short circuit is 6.8% of D max (97.9%), or ~6.6%.
Performance
The major performance criteria for the converter are efficiency, and to a lesser extent, load regulation. Efficiency, load regulation and line regulation performance are demonstrated in the following Figures.
100 EFFICIENCY (%) 95 90 85 80 75 70 0 1 2 3 4 5 6 LOAD CURRENT (A) 7 8 9
FIGURE 13. OUTPUT SOFT START
FIGURE 10. EFFICIENCY vs LOAD VIN = 48Vt
Figure 14 shows the output voltage ripple and noise at a 5A load.
12.5 OUTPUT VOLTAGE (V) 12.25 12 11.75 11.5 11.25 11 0 1 2 3 4 5 6 LOAD CURRENT (A) 7 8 9
FIGURE 11. LOAD REGULATION AT VIN = 48V
14 OUPUT VOLTAGE (V) 13.5 13 12.5 12 11.5 11 45 46 47 48 49 50 51 52 INPUT VOLTAGE (V) 53 54
FIGURE 14. OUTPUT RIPPLE AND NOISE - 20MHz BW
FIGURE 12. LINE REGULATION AT IOUT = 1A
As expected, the output voltage varies considerably with line and load when compared to an equivalent converter with closed loop feedback. However, for applications where tight
Figures 15 and 16 show the voltage waveforms at the switching node shared by the upper FET source and the lower FET drain. In particular, Figure 16 shows near ZVS operation at 8A of load when the upper FET is turning off and the lower FET turning on. There is insufficient energy stored in the leakage inductance to allow complete ZVS operation. However, since the energy stored in the node capacitance is proportional to V2, a significant portion of the energy is still recovered. Figure 17 shows the switching transition between outputs, OUTA and OUTB during steady state operation. The deadtime duration of 48.6ns is clearly shown.
20
ISL6740, ISL6741 Component List
REFERENCE DESIGNATOR VALUE C1 C2, C3 C4, C6 1.0F 3.3F 1.0F DESCRIPTION Capacitor, 1812, X7R, 100V, 20% TDK C4532X7R2A105M Capacitor, 1812, X5R, 50V, 20% TDK C4532X5R1H335M Capacitor, 0805, X5R, 16V, 10% TDK C2012X5R1C105K Capacitor, 0603, X7R, 50V, 10% TDK C1608X7R1H104K Capacitor, 0603, Open Capacitor, 1812, X5R, 16V, 20% TDK C4532X5R1C226M Capacitor, Radial, Sanyo 16SH150M
C5, C15, C16 0.1F C7 C8 FIGURE 15. FET DRAIN-SOURCE VOLTAGE C9 Open 22F 150F
C10, C11, 1000pF Capacitor, 0603, X7R, 50V, 10% C12, C13, C14 TDK C1608X7R1H102K C17 C18 CR1, CR2 CR3 D1 L1 L2 L3 Q5 QL, QH FIGURE 16. FET D-S VOLTAGE NEAR-ZVS TRANSITION QR1, QR2, QR3, QR4 R1, R10 R2 R3, R6 R5 R7 R8, R9 R11 R12 R13 R14 R15 R17 R18 R19, RT1 T1 FIGURE 17. OUTA - OUTB TRANSITION T2 U1 U3 3.3 3.01K 10.0 3.32 75.0K 20.0 100 8.06K 17.4K Open 1.27K 97.6K 3.01K 10.0K 190nH 1.5H Short 220pF Capacitor, 0603, COG, 16V, 5% TDK C1608COG1C221J
0.047F Capacitor, 0603, X7R, 16V, 10% TDK C1608X7R1C473K Diode, Schottky, BAT54S Diode, Schottky, BAT54 Zener, 10V, Philips BZX84C10ZXCT-ND Pulse, P2004T Pulse, PG0077.142 Jumper or Optional Discrete Leakage Inductance Transistor, ON MJD31C FET, Fairchild FDS3672 FET, Fairchild FDS5670 Resistor, 2512, 5% Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0805, 1% Resistor, 0805, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, Open Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Midcom 31718 Pulse P8205T Intersil HIP2101IB ISL6740IB
21
ISL6740, ISL6741
Adding Line Only Regulation - Feed Forward
Output voltage variation caused by changes in the supply voltage may be virtually removed through a technique known as feed forward compensation. Using feed forward, the duty cycle is directly controlled based on changes in the input voltage only. No closed loop feedback system is required. Voltage feed forward may be implemented as shown below.
R109 3.48K VREF 1.5V +VIN 0.8V R110 698 R111 806
Other duty ranges are possible, but are still limited to a 2:1 ratio. The voltage applied to VERROR must be scaled to the peak-to-peak voltage on CT, and offset by the valley voltage. Since the peak-to-peak CT voltage is 2.00V nominal, the voltage at the output of U100A must be divided by 2.0V to obtain the desired duty cycle. For example, if an 80% duty cycle was required at the minimum operating voltage, the output of U100A must be 1.60V (80% of 2.00V). From (EQ. 25), the divider voltage must be set to 1.4V for the input voltage that corresponds to the 80% duty cycle. It should be noted that the synchronous rectifiers (SRs), being driven from the transformer secondary, are only gated on during the ON time of the primary FETs. Conduction continues through the body diodes during the OFF time when operating in continuous inductor current mode. This mode of operation usually results in significant conduction and switching losses in the SR FETs. These losses may be reduced considerably by either adding schottky diodes in parallel to the SR FETs or by driving the SR FETs directly with a control signal.
R100 69.8K
R103 49.9K + R102 100K R104 100K U100A R105 100K
R106 100K
U100B + -
to VERROR
R101 2K
R107 100K C100 1nF R108 100K
Adding Regulation - Closed Loop Feedback
The second Typical Application schematic adds closed loop feedback with isolation. The ISL6740EVAL2 demonstration platform implements this design and is available for evaluation. The input voltage range was increased to 36V 75V, which necessitates a few modifications to the open loop design. The output inductor value was increased to 4.0H, schottky rectifier CR4 was added to minimize SR FET body diode conduction, the turns ratio of the main transformer was changed to 4:3, and the synchronous rectifier gate drives were modified. The design process is essentially the same as it was for the unregulated version, so only the feedback control loop design will be discussed. The major components of the feedback control loop are a programmable shunt regulator and an opto-coupler. The opto-coupler is used to transfer the error signal across the isolation barrier. The opto-coupler offers a convenient means to cross the isolation barrier, but it adds complexity to the feedback control loop. It adds a pole at about 10kHz and a significant amount of gain variation due the current transfer ratio (CTR). The CTR of the opto-coupler varies with initial tolerance, temperature, forward current, and age.
FIGURE 18. VOLTAGE FEED FORWARD CIRCUIT
The circuit provides feed forward compensation for a 2:1 input voltage range. Resistors R100 and R101 set the input voltage divider to generate a 1.00 volt signal at the input voltage that corresponds to maximum duty cycle (VIN minimum). Resistors R109, R110, and R111 form a voltage divider from VREF to create reference voltages for the amplifiers. The first stage uses U100A, R102, R103, R104, and C100 to form a unity gain inverting amplifier. Its output varies inversely with input voltage and ranges from 1 to 2V. The bandwidth of the circuit may be controlled by varying the value of C100. The gain of the first amplifier stage is:
V A = - V D + 3.00 V (EQ. 25)
where: VA = Output voltage of U100A VD = The input divider voltage The second stage uses U100B, R105, R106, R107, and R108 to form a summing amplifier which offsets the first stage output by 0.8V (the value of CT valley voltage). The signal applied to the VERROR input now matches the offset and amplitude of the oscillator sawtooth so that the duty cycle varies linearly from 100% to 50% of maximum with a 2:1 input voltage variation.
22
ISL6740, ISL6741
A block diagram of the feedback control loop follows in Figure 19.
40 30 PWM POWER STAGE 20 GAIN (dB) 10 0 -10 -20
VOUT
ERROR AMPLIFIER Z2 + REF Z1
ISOLATION
10
100
1*103 1*104 FREQUENCY (Hz)
1*105
1*106
FIGURE 19. CONTROL LOOP BLOCK DIAGRAM
FIGURE 21A. CONTROL-TO-OUTPUT GAIN
50
The loop compensation is placed around the Error Amplifier (EA) on the secondary side of the converter. A Type 3 error amplifier configuration was selected.
PHASE (DEGREES) VOUT
0
-50
-100
-
VERR
+
REF
-150
-200 10 100
FIGURE 20. TYPE 3 ERROR AMPLIFIER
1*103 1*104 FREQUENCY (Hz)
1*105
1*106
FIGURE 21B. CONTROL-TO-OUTPUT PHASE
The control to output transfer function may be represented as [1]
s 1 + -----z NS V IN vo ----- = ---------------- * ------- * -----------------------------------------------VS * 2 NP vc s2 s 1 + ---------------- + ------ ( Q ) o o
(EQ. 26)
The Type 3 compensation configuration has three poles and two zeros. The first pole is at the origin, and provides the integration characteristic which results in excellent DC regulation. Referring to the Typical Application Schematic for the regulated output, the remaining poles and zeros for the compensator are located at:
1 f p2 = ---------------------------------------2 * R21 * C20 1 f p3 ------------------------------------2 * R4 * C22 C19 C20 (EQ. 27)
where
Ro Q = --------------o * L 1 o = ----------LC 1 z = ----------Rc C or 1 f o = ------------------2 LC 1 f z = -----------------2R c C
(EQ. 28)
or
1 f z1 = ---------------------------------------2 * R21 * C19 1 f z2 ---------------------------------------2 * R23 * C22 R23 R4
(EQ. 29)
Ro = Output Load Resistance L = Output Inductance C = Output Capacitance Rc = Output Capacitance ESR VS = Sawtooth Ramp Amplitude Gain and phase plots of (EQ. 26) appear below using L = 4.0H, C = 150F, Rc = 28m, Ro = 1.2, and Vin = 75V.
(EQ. 30)
From (EQ. 26), it can be seen that the control to output transfer function frequency dependence is a function of the output load resistance, the value of output capacitor and inductor, and the output capacitance ESR. These variations must be considered when compensating the control loop. The worst case small signal operating point for a voltage mode converter tends to be at maximum Vin, maximum load, maximum Cout, and minimum ESR.
23
ISL6740, ISL6741
The higher the desired bandwidth of the converter, the more difficult it is to create a solution that is stable over the entire operating range. A good rule of thumb is to limit the bandwidth to about Fsw/4, where Fsw is the switching frequency of the converter. However, due to the bandwidth constraints of the opto-coupler and the LM431 shunt regulator, the bandwidth was reduced to about 25kHz. The first pole is placed at the origin by default (C20 is an integrating capacitor). If the two zeroes are placed at the same frequency, they should be placed at fLC/2, where fLC is the resonant frequency of the output L-C filter. To reduce the gain peaking at the L-C resonant frequency, the two zeroes are often separated. When they are separated, the first zero may be placed at fLC/5, and the second at just above fLC. The second pole is placed at the lowest expected zero cause by the output capacitor ESR. The third, and last pole is placed at about 1.5 times the cross over frequency. Some liberties where taken with the generally accepted compensation procedure described above due to the transfer characteristics of the opto coupler. The effects of the opto-coupler tend to dominate over those of the LM431 so the GBWP effects of the LM431 are not included here. The gain and phase characteristics of the opto coupler are shown below.
10 10 5 0 GAIN (dB) -5 -10 -15 -20 10 100 -10 10 100 1*103 1*104 1*105 1*106 GAIN (dB) 0
The following compensation components were selected R23 = 9.53k R24 = 2.49k R4 = 499 R21 = 4.22k C22 = 1nF C20 = 82pF C19 = 0.22F From (EQ. 27-30), the poles and zeroes are: fz1 = 171Hz fz2 = 16.7kHz fp2 = 460kHz fp3 = 319kHz The calculated gain and phase plots of the error amplifier appear below using an ideal op amp.
20
FREQUENCY (Hz)
FIGURE 23A. IDEAL ERROR AMPLIFIER GAIN
1*103 1*104 1*105 1*106 90 FREQUENCY (Hz)
FIGURE 22A. OPTO COUPLER GAIN
90
PHASE (DEGREES)
45
PHASE (DEGREES)
45
0
0
-45
-45
-90 10 100
1*103
1*104
1*105
1*106
FREQUENCY (Hz) -90 10 100 1*103 1*104 1*105 1*106
FIGURE 23B. IDEAL ERROR AMPLIFIER PHASE
FREQUENCY (Hz)
FIGURE 22B. OPTO COUPLER
24
ISL6740, ISL6741
The gain and phase plots combined with the opto coupler's transfer characteristics appear below:
30
Using the control-to-output transfer function combined with the EA transfer function, the loop gain and phase may be predicted. The predicted loop gain and phase margin of the converter appear below:
50
20 GAIN (dB)
40 30 20 GAIN (dB) 100 1*103 1*104 1*105 1*106 FREQUENCY (Hz)
10
10 0 -10 -20 -30
0
-10 10
-40 -50 100 1*103 1*104 FREQUENCY (Hz) 1*105
FIGURE 24A. EA PLUS OPTO COUPLER GAIN
FIGURE 25A. PREDICTED LOOP GAIN
90 45 PHASE (DEGREES) PHASE MARGIN (DEGREES) 0 -45 -90 -135 -180 10
225 180 135 90 45 0 -45 -90 -135 100 1*103 1*104 1*105
100
1*103 1*104 FREQUENCY (Hz)
1*105
1*106
FIGURE 24B. EA PLUS OPTO COUPLER GAIN
FREQUENCY (Hz)
FIGURE 25B. PREDICTED LOOP PHASE MARGIN
25
ISL6740, ISL6741
The actual loop gain and phase margin measured on the ISL6740EVAL2 demonstration board appear below:
50 40 30 20 GAIN (dB) 10 EFFICIENCY (%) 1 10 100 85 2 3 4 5 6 7 8 9 10 LOAD CURRENT (A) FREQUENCY (kHz) OUTPUT VOLTAGE (V) 0 -10 -20 -30 -40 -50 0.1 93 91 89 87 95
Performance
The major performance criteria for the converter are efficiency and load regulation. These quantities are detailed in the following Figures.
FIGURE 26A. MEASURED LOOP GAIN FIGURE 27. EFFICIENCY vs LOAD VIN = 48Vt
225 PHASE MARGIN (DEGREES) 180 135 90 45 0 -45 -90 -135 0.1 1 10 100
12.015
12.01
12.005
12
FREQUENCY (kHz)
11.995
0
1
2
3
4
5
6
7
8
9
10
FIGURE 26B. MEASURE LOOP PHASE MARGIN
LOAD CURRENT (A)
The only major discrepancies between the predicted behavior and the measured results are the Q of the L-C filter and the phase behavior above 60kHz. The actual Q appears to be significantly less than predicted resulting in less gain peaking and a less rapid phase shift near the resonant frequency. This is most likely the result of neglecting other losses in the converter's output, such as the FET on resistance, copper losses, and inductor resistance. The phase discrepancy above 60kHz is not particularly relevant to the loop performance since it occurs well above the cross over frequency. The predicted behavior indicates a much gentler drop off of phase than was observed in the measured performance. The discrepancy was not investigated.
FIGURE 28. LOAD REGULATION AT VIN = 48V
The efficiency, although very good, could be further improved using a controlled SR method instead of using a self-driven method with an auxiliary schottky diode. The schottky diode conducts when the main switching FETs are off. Its forward voltage drop is considerably larger than that of the SR FETs and causes a measurable reduction in efficiency. The effect becomes more significant as the input voltage is increased due to the reduction of duty cycle (and consequent increase in the OFF time).
26
ISL6740, ISL6741 Component List
REFERENCE DESIGNATOR VALUE C1 C2, C3 C4, C6 C5, C15, C16 C7 C8, C21 C9 1.0F 3.3F 1.0F 0.1F Open 22F 150F DESCRIPTION Capacitor, 1812, X7R, 100V, 20% TDK C4532X7R2A105M Capacitor, 1812, X5R, 50V, 20% TDK C4532X5R1H335M Capacitor, 0805, X5R, 16V, 10% TDK C2012X5R1C105K Capacitor, 0603, X7R, 50V, 10% TDK C1608X7R1H104K Capacitor, 0603, Open R15 Capacitor, 1812, X5R, 16V, 20% TDK C4532X5R1C226M Capacitor, Radial, Sanyo 16SH150M Capacitor, 0603, X7R, 50V, 10% TDK C1608X7R1H102K Capacitor, 0603, X7R, 100V, 10% TDK C1608X7R2A561K Capacitor, 0603, X7R, 100V, 10% TDK C1608X7R2A221K Capacitor, 0603, COG, 16V, 5% TDK C1608COG1C221J R16, R19 R17 R18 R20 R21 R23 R24 R26, R27 RT1 T1 T2 U1 U2 U3 CR1, CR2 CR3, CR5, CR6 CR4 D1 D2 L1 L2 L3 Q5 QL, QH, QR1, QR2, QR3, QR4 R1 R2 R3 R4, R25 R5 3.3 3.01K 10.0 499 2.20 190nH 4.0H Short Diode, Schottky, BAT54S U4 Diode, Schottky, BAT54 Diode, Schottky, IR 12CWQ06FN Zener, 10V, Philips BZX84C10ZXCTND Zener, 6.8V, Philips BZX84C6Z8XCTND Pulse, P2004T BI Technologies, HM65-H4R0 0 Ohm Jumper Transistor, ON MJD31C FET, Fairchild FDS3672 National LM431BIM3/N1C 1.27K 1.00K 97.6K 3.01K 2.00K 4.22K 9.53K 2.49K 5.11 10.0K Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0805, 1% Resistor, 0603, 1% Midcom 31660 Pulse P8205T Intersil HIP2101IB NEC PS2801-1 ISL6740IB
Component List (Continued)
REFERENCE DESIGNATOR VALUE R6 R7 R8, R9, R10 R11 R12 R13 R14 200 75.0K 18 205 8.06K 18.2K Open DESCRIPTION Resistor, 0603, 1% Resistor, 0805, 1% Resistor, 2512, 5% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, Open
C10, C14, C22 1000pF C11, C12 C13 C17 C18 C19 C20 560 pF 220pF 220pF
0.047F Capacitor, 0603, X7R, 16V, 10% TDK C1608X7R1C473K 0.22F 82pF Capacitor, 0603, X7R, 16V, 10% TDK C1608X7R1C224K Capacitor, 0603, X7R, 16V, 10% TDK C1608X7R1C820K
References
[1] Dixon, Lloyd H., "Closing the Feedback Loop", Unitrode Power Supply Design Seminar, SEM-700, 1990.
Resistor, 2512, 5% Resistor, 2512, 2% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0805, 1%
27
ISL6740, ISL6741 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 NOTES 9 3 4 6 7 8o Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC 0.246 0.020 16 0o 8o 0.256 0.028
0.65 BSC 6.25 0.50 16 0o 6.50 0.70
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
28
ISL6740, ISL6741 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1 B MIN 0.053 0.004 0.014 0.007 0.386 0.150 MAX 0.069 0.010 0.019 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.35 0.19 9.80 3.80 MAX 1.75 0.25 0.49 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 1 02/02
L
C D E e H h
C
0.050 BSC 0.228 0.010 0.016 16 0o 8o 0.244 0.020 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS

A1 0.10(0.004)
L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 29

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